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Lattice Semiconductor
PCI Express User’s Guide
Port Name
Active State
I/O
Signal Description
RX_USR Interface
rxtlpu_data[31:0]
rxtlpu_st
rxtlpu_sd
rxtlpu_end
rxpm_dllp_type
rxpm_dllp_val
pois_tlp
un_sup_req
malf_tlp
bad_tlp
bad_dllp
dll_perr
rnum_rlor
rply_tout
—
High
High
High
—
High
High
High
High
High
High
High
High
High
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Received TLP Data to Transaction Layer
Start of Received TLP on the “rxtlpu_data”
Start of Data in the Received TLP
End of TLP on the “rxtlpu_data”
Type of Received PM DLLP
Valid Signal to Sample “rxpm_dllp_type”
Poisoned TLP received indication
Unsupported Request Received Indication
Malformed TLP Received Indication
Bad TLP Received Indication
Bad DLLP Received Indication
Data Link Layer Protocol Error Indication
REPLY_NUM Rollover Indication
Replay Timer Timeout Indication
TX_USR Interface
txtlpu_req
txtlpu_data[31:0]
txtlpu_st
txtlpu_end
txtlpu_nlfy
no_pcie_training
pkt_type
txpm_dllp_type
tx_pm
l_retrain_link
l_ext_sync
High
—
High
High
High
High
—
—
High
High
High
I
I
I
I
I
I
I
I
I
I
I
User Interface Request to Send TLPs
TLP Data to be Transmitted on PCI Express Link
Start of TLP Signal that Indicates Start of New TLP on the txtlpu _data
Bus
End of TLP Signal that Indicates End of TLP on the txtlpu _data Bus
User Interface Request to Generate a Nulli?ed TLP This Signal is to be
Asserted Along With End of TLP
No LTSSM Training to be performed
Packet type for credit info
PM packet type to transmit
Send PM DLLP, with PM data in “ tx_data ”
Initiate Link Retraining
Extended syn
Link Control bits from User Interface
Bit 0 – Set Hot_Reset bit in TS1/TS2 Will switch the Core to Reset state if
current state is Recovery
loc_lnk_cntl[3:0]
High
I
Bit 1 – Set Disable_Link bit in TS1/TS2 Will switch the Core to Disable state
if current state is Recovery
Bit 2 – Set Loopback bit in TS1/TS2 Will switch the Core to Tx_Loopback
state if current state is Recovery
Bit 3 – Set Disable_scramble bit in TS1/TS2
l_go_config
txtlp_rdy
crdt_avail
High
High
—
I
O
O
Direct the Core to Switch to Con?guration State
The Data Link Layer is Ready to Accept TLPs from Transaction Layer
Credit Available for the Packet Type
Note2:
1. For all PCI Express Line Interface signals (both input and output) refer to the ORT42G5 and ORT82G5 data sheet for their usage.
2. External Circuit Interface: rx_detect signal to be generated by an external circuit whenever the start_rx_detect signal is asserted.
Refer to the Receiver Detection section in “PHY Interface for the PCI Express Architecture”.
3. For usage of loc_lnk_cntl and l_go_config signals refer to the Link Training and Status State Machine section of the PCI Express
speci?cations.
14
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